Dedicated Runs and Capabilities in Development

Dedicated Runs

In addition to MPW runs, we also offer dedicated or custom runs. There are many more fabrication options available in dedicated runs compared to MPW runs. A list of the options currently available in our dedicated runs is shown below. Dedicated runs are also an excellent option for larger volumes of chips or fabrication of devices on custom substrates. Since dedicated runs can begin at any time, the timing of dedicated runs is more flexible than MPW runs.

To begin a dedicated run, please contact us at support@appliednt.com and specify which fabrication options you would like to include. We will develop a custom fabrication plan, timeline, and quotation for your project. Unlike MPW runs, the costs of a dedicated run are not spread across multiple customers, and so it is often beneficial to fabricate more than one chip on a dedicated run.

If there is a fabrication process you are interested in that is not listed here, please email us! It may be possible to fabricate your device as we are always developing new processes and capabilities.

Dedicated Run Options

We have many options available for custom runs. It is possible to combine many of these with standard MPW options such as direct metallization, tri-layer metallization, and deep trenches. Currently available dedicated fabrication options are listed here:

  • Custom cladding oxide thickness
    We can deposit cladding oxide thicknesses up to 3 μm. Typical oxide thicknesses are 1 μm and 2.2 μm.

  • Different silicon device layer thickness
    We have SOI wafers with the following device layer thicknesses: 145 nm, 220 nm, 300 nm, and 500 nm. As the device layer thickness increases, the minimum feature size and spacing increase to maintain a suitable aspect ratio.

  • Multi-layer alignment with 50 nm accuracy
    Multi-layer alignment can be used to accurately place metal features or create partially-etched silicon structures such as rib waveguides.

  • Positive-tone structures
    Positive tone structures include photonic crystal cavities.

  • Multiple silicon etch depths
    We can etch partially into the silicon to create structures such as rib waveguides and gratings. The etch depth can be customized, and the error in the etch depth is ± 10 nm.

  • Oxide via etching
    Windows in the cladding oxide allow for electrical connections to metal layers fabricated using the standard direct metallization option. The metal layers are deposited directly on the silicon or buried oxide layers. The window in the oxide, called the oxide via, must terminate on a metal layer.

  • Selective buried oxide etching
    The buried oxide layer can be used as a sacrificial material for micro- or nanomechanical devices. By selectively removing the buried oxide, we can release mechanical devices for optomechanics and other applications.

  • Custom metal levels and choices of metals
    We have many custom metals available including Cr, Au, Al, TiW, W, and Ni. When combined with the custom oxide cladding option, these metals can be placed at any oxide depth for electrical circuits or custom heaters.

  • Thermal isolation trenches
    By etching through the cladding and buried oxide, and isotropically into the silicon handle, we can create thermal isolation trenches that can be used to improve the performance of thermo-optic switches.

  • Through-cladding windows
    We etch through the oxide cladding to create windows that open onto the silicon or buried oxide layers.

  • Deep trench with full silicon handle etch
    A variation on the standard deep trench process. We perform a deep silicon etch during the deep trench process to etch fully through the silicon handle layer. The end result is a smooth chip edge from the top of the cladding to the bottom of the handle. This is useful when fiber arrays with large dimensions are required for edge coupling.

  • Fiber bonding service
    Attachment of 2, 4 and 8-fiber arrays onto dies for light input/output.

  • Measurement services
    In-house semi-automatic measurement of vertically coupled devices in C-band.

Capabilities in Development

We are working on the following capabilities:

  • Bonded photodetectors
    Epoxy-bonded InGaAs photodiode arrays for use with strip waveguides, ready for wire-bonding.

  • Four-level ion implantation (N++, N, P++, P) and defect-based detectors
    Ion implantation may be used for on-chip photodetectors or modulators based on the free carrier effect.

  • Silicon nitride waveguides
    Silicon nitride waveguides may be used in applications where low-contrast waveguides are required.