The foundation of the NanoSOI fabrication process is the device layer. Photonic waveguides capable of light propagation are patterned using 100 keV electron beam lithography technology. Fully-etched devices (etched down to the buffer oxide, as shown in the above diagram) are created using an e-beam mask material and anisotropic ICP-RIE etching process. The minimum feature size is 120 nm and the minimum feature spacing is 120 nm, where duty cycle of surrounding region is ≤ 50%. For duty cycles greater than 50%, resolution will decrease further because of proximity effects.
|Device Layer Type||Device Layer Thickness||Buffer Oxide Layer Thickness||Silicon Handle (Substrate) Thickness||Wafer Manufacturer|
|Silicon nitride (SixNy)||400 nm||4.5 μm||525 μm||Applied Nanotools fabricates the SixNy on WaferPro wafers|
Applied Nanotools measures the optical propagation loss on each run using the cutback method. The test structures are strip waveguides with varying lengths and widths. The cladding is 3.0 μm thick silicon dioxide. The transmission of each device is measured, and the propagation loss is calculated by performing a linear fit of transmission in dB versus the waveguide length. Both straight and curved waveguide segments are used. These results are averaged over two sets of test arrays per run. We maintain a running average over time, and display the most up-to-date propagation loss results for fully-etched 400 nm silicon nitride waveguides in the table below:
|Waveguide Width||Straight Waveguide Loss||Curved Waveguide Loss|
|0.75 μm||1.5 dB/cm||5 dB/cm|
|1 μm||1.4 dB/cm||4.4 dB/cm|
Detailed measurement data, including spectral scans, can be provided by request.
A limitation of electron beam lithography technology is electron scattering effects when exposing patterns into the mask. During the file preparation process, we apply a proximity effect correction algorithm to the design to mitigate these effects. However, extreme cases such as large areas/pads (> 10 × 10 μm) in close proximity to high-resolution features or small feature spacings are difficult to correct for. Please inquire with us if your design has large areas to be exposed in conjunction with high resolution features or small spacings. For regions with duty cycle (pattered area ÷ total area) larger than 50%, the minimum dimension and minimum spacing will be larger than what is specified in the design rules. The examples below show acceptable designs (green check mark) and designs with duty cycles greater than 50% (red X).
Due to the nature of the etching process, the silicon nitride features will have an angle to the sidewall. The sidewall angle of silicon nitride features fabricated with our process is approximately 83.5 degrees with a standard deviation of 0.5 degrees. The dimensions drawn on the GDS design file occur at approximately 50% of the waveguide height with a standard deviation of 7%. In nanometers, this correlates to 200 nm with a standard deviation of 28 nanometers. This is illustrated for clarity in the waveguide cross-section schematic below.
Thinner custom oxide cladding can be requested on dedicated runs. Please contact firstname.lastname@example.org to inquire.
|Metal||Thickness||Bulk Resistivity||Sheet Resistance|
|200 nm||0.61 μΩ-m||3.07 Ω/sq.|
|200 nm TiW + 500 nm Al||0.04 μΩ-m||0.08 Ω/sq.|