Design Rules and Area

  This area contains important rules and specifications for projects submitted to our NanoSOI multi-project wafer (MPW) runs. Failure to follow the design rules for each layer/option may result in defects in the fabricated devices.

Design Rules

The following table summarizes the design rules for each layer available in the NanoSOI Silicon MPW runs.

Layer Number Process Minimum Feature Size Minimum Feature Spacing Design Area Notes
1 Silicon full etch 60 nm lines 70 nm lines 9 mm x 9 mm Feature sizes specified where duty cycle of surrounding region is ≤ 50%. See example here.
1 Silicon full etch IF both air cladding and deep trench are required 100 nm lines 100 nm lines 9 mm x 9 mm If air cladding and deep trench are required, the silicon feature size increases to improve yield. For questions contact Support.
5 Direct metallization 5 μm 10 μm Standard layout is 9 mm x 9 mm. Deep trench layout is 8.4 mm x 8.4 mm --
6 Through-cladding windows N/A N/A Requires prior approval to use. Please inquire with Support --
11 Tri-layer metal: TiW alloy 3 μm 3 μm Standard layout is 9 mm x 9 mm. Deep trench layout is 8.4 mm x 8.4 mm --
12 Tri-layer metal: TiW/Al Bilayer 5 μm 8 μm Standard layout is 9 mm x 9 mm. Deep trench layout is 8.4 mm x 8.4 mm --
13 Tri-layer metal: Bond pad open 10 μm 10 μm Standard layout is 9 mm x 9 mm. Deep trench layout is 8.4 mm x 8.4 mm Must be placed over Layer 12.
189 Custom dicing 100 μm 3 mm 9 mm x 9 mm 50 μm spacing to devices. See example here.
200 SEM imaging 500 nm wide None 9 mm x 9 mm Only rectangular boxes with aspect ratio 4:3 (width to height). See example here.
201 Deep trench 260 μm 3 mm 8.78 mm x 8.78 mm 35 μm spacing to metal. Only extend Layer 1 edge couplers into Layer 201. See examples here and here.
202 Deep trench exclusion layer 3 mm x 200 μm 3 mm -- Required for deep trench layouts. Exclusion layer to allow for chip handling. See example here.
203 Thermal isolation trenches 15 μm 15 μm 8.78 mm x 8.78 mm 15 μm spacing to metal. 10 μm spacing to silicon. See example here.


The image above shows the correlation of the layer numbers to each physical layer in the fabrication process. A layer definition file containing the NanoSOI layer information is available for download below. You can import the layer definition file into KLayout by choosing File, then Load Layer Properties. Design examples for tri-layer metallization, deep trench, thermal isolation trenches, and the SEM imaging layer are also available. All of our tutorials are designed to match the Layer Definition file.


  Download Layer Definitions

Physical Chip Size and Design Area

In our MPW runs, chips are fabricated on larger substrates, then singulated into individual chips with a physical footprint of 10 mm x 10 mm. The space reserved for your actual design is a 9.0 mm x 9.0 mm area. The placement of this bounding box is at the origin (x=0, y=0) of the GDSII design and extends to -4500 and +4500 in X/Y as shown below: