Design Rules and Area

  This area contains important rules and specifications for projects submitted to our NanoSOI multi-project wafer (MPW) runs. Failure to follow the design rules for each layer/option may result in defects in the fabricated devices.

Design Rules

The following table summarizes the design rules for each layer available in the NanoSOI MPW runs.

Layer Number Process Minimum Feature Size Minimum Feature Spacing Design Area Notes
1 Silicon full etch 60 nm 60 nm 9 mm x 9 mm Feature sizes specified where duty cycle of surrounding region is ≤ 50%. See example here.
5 Direct metallization 10 μm 20 μm Standard layout is 9 x 9 mm. Deep trench layout is 8.4 x 8.4 mm --
11 Tri-layer metal: TiW alloy 3 μm 3 μm Standard layout is 9 x 9 mm. Deep trench layout is 8.4 x 8.4 mm Minimum overlap with Layer 12 is 3 μm.
12 Tri-layer metal: TiW/Al Bilayer 5 μm 10 μm Standard layout is 9 x 9 mm. Deep trench layout is 8.4 x 8.4 mm Minimum overlap with Layer 11 is 3 μm.
13 Tri-layer metal: Oxide windows 10 μm 10 μm Standard layout is 9 x 9 mm. Deep trench layout is 8.4 x 8.4 mm Must be placed over Layer 12.
200 SEM imaging 500 nm wide None 9 mm x 9 mm Only rectangular boxes with aspect ratio 4:3 (width to height). See example here.
201 Deep trench None None 8.78 mm x 8.78 mm Layer 201 is a floor plan layer only. Only extend Layer 1 edge couplers into Layer 201. See example here.
202 Deep trench exclusion layer 3 mm x 200 μm 8.38 mm -- Required for deep trench layouts. Exclusion layer to allow for chip handling.. See example here.


The image above shows the correlation of the layer numbers to each physical layer in the fabrication process. A layer definition file containing the NanoSOI layer information is available for download below. You can import the layer definition file into KLayout by choosing File, then Load Layer Properties. Design examples for tri-layer metallization, deep trench, and the SEM imaging layer are also available. All of our tutorials are designed to match the Layer Definition file.


  Download Layer Definitions

Physical Chip Size and Design Area

In our MPW runs, chips are fabricated on larger substrates, then singulated into individual chips with a physical footprint of 10 x 10 mm. The space on the chip is dedicated to both your design, and also to a series of calibration and alignment marks that are used for various process options and quality control. The space reserved for your actual design is a 9.0 x 9.0 mm area:


Therefore, the data extents of your design cannot extend further than a 9.0 x 9.0 mm area. The placement of this bounding box is at the origin (x=0, y=0) of the GDSII design and extends to -4500 and +4500 in X/Y as shown below: