The foundation of the NanoSOI fabrication process is the device layer. Photonic waveguides capable of light propagation are patterned using 100 keV electron beam lithography technology. In our multi-project wafer runs, fully-etched devices (etched down to the buffer oxide, as shown in the above diagram) are created using an e-beam mask material and anisotropic ICP-RIE etching process. The minimum feature size is 60 nm and the minimum feature spacing is 70 nm, where duty cycle of surrounding region is ≤ 50%. For duty cycles greater than 50%, resolution will decrease further because of proximity effects.
We currently offer one substrate in our multi-project wafer (MPW) runs:
|Device Layer Type||Device Layer Thickness||Buffer Oxide Layer Thickness||Silicon Handle (Substrate) Thickness||Wafer Manufacturer|
|Silicon||220 nm||2.0 μm||725 μm||SOITEC S.A.|
Applied Nanotools periodically measures the optical propagation loss using test structures. The test structure is a straight 500 nm-wide silicon strip waveguide with a 2.2 μm thick cladding oxide. Cut-back loss measurements are performed by varying the length of the waveguide from 0 to 3 centimetres, measuring the total insertion loss of each device and performing a linear fit on loss vs. waveguide length. Both straight and curved waveguide segments are used. The average propagation loss for fully-etched 220 nm SOI devices is tabulated below:
|Polarization||Straight Waveguide Loss||Curved Waveguide Loss|
|TE||1.5 dB/cm||3.5 dB/cm|
|TM||2.0 dB/cm||2.5 dB/cm|
These results are averaged over two sets of test arrays. Each set was separated by 9 mm. Detailed measurement data, including spectral scans, can be provided by request.
A limitation of electron beam lithography technology is electron scattering effects when exposing patterns into the mask. During the file preparation process, we apply a proximity effect correction algorithm to the design to mitigate these effects. However, extreme cases such as large areas/pads (> 10 × 10 μm) in close proximity to high-resolution features or small feature spacings are difficult to correct for. Please inquire with us if your design has large areas to be exposed in conjunction with high resolution features or small spacings. For regions with duty cycle (pattered area ÷ total area) larger than 50%, the minimum dimension and minimum spacing will be larger than what is specified in the design rules. The examples below show acceptable designs (green check mark) and designs with minimum features greater than 60 nm (red X).
Imperfections in the mask and etching process will create an angle to the sidewall of the waveguide. The sidewall angle of silicon waveguides fabricated with our process is approximately 88 degrees (improved from 82 degrees, prior to the January 2021 MPW run). We aim to have the waveguide dimensions match the GDS design with proximity and etch bias corrections applied during layout processing.
Custom oxide thicknesses up to 3 µm can be requested but are subject to an additional surcharge. Please contact firstname.lastname@example.org to inquire.
(with 4 nm Cr adhesion layer)
|Metal||Thickness||Bulk Resistivity||Sheet Resistance|
|200 nm||0.61 μΩ-m||3.04 Ω/sq.|
|200 nm TiW + 500 nm Al||0.04 μΩ-m||0.07 Ω/sq.|